The NAND gate is monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge and latching conditions. Features:- Two Independent 4-input NAND Gates Standard Pin Configuration Wide Operating Voltage Range Operating Temperature to 85°C Low Power CMOS Specifications:- Parameter Specification Voltage at Any Pin VSS -0.3V to VDD 0.3V Operating Temperature Range -40°C to 85°C Storage Temperature Range (TS) -65°C to 150°C Power Dissipation (PD): Dual-In-Line 700 mW Operating Range (VDD) VSS 3.0V to VSS 15V Lead Temperature (TL) 260°C (For detailed specification refer Data Sheet) Related Document:- CD4012 IC Datasheet
